In modern analog circuit simulation, the topology and behavior of circuits are usually described in the form of netlists, where the parameters of the simulated devices can be specified as fixed numbers as well as dynamic expressions. Especially in modern technology nodes, these expressions are used exhaustively to model even the smallest physical effects, i.e., the expressions define the characteristics of the circuit elements. These characteristics can depend on the circuit variables, which are the unknowns of the simulation. These expressions are interpreted in each simulation loop during the circuit simulation to determine the correct parameter values. Unfortunately, this interpretation of expressions is a performance bottleneck.

This thesis investigates various approaches to expression evaluation in the context of a circuit simulator. It introduces a Just-in-Time (JIT) compilation approach for compiling expressions to machine code for evaluations. As a first step, an expression evaluation engine has been developed as an independent library. The engine provides infrastructure for parsing using the C++ library PEGTL, semantic analysis, type inference, LLVM-IR code generation, JIT compilation using LLVM Orc JIT, and JIT-compiled function calls using libffi. Afterwards, the expression evaluation engine is integrated into a SPICE-based analog circuit simulator. Finally, for a set of test circuits, the runtime performance of the circuit simulator with the expression evaluation engine is compared. The benchmark results show that for setup with profuse use of dynamic expressions, there is up to 45% speedup in the total simulator runtime.