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Mohammadreza Najafi received his B.Sc. and M.Sc. degrees from University of Tehran, Iran, in 2009 and 2012 in the fields of Hardware Engineering and Computer Architecture. His M.Sc. thesis topic was “Communication Customization on MPSoCs,” which aimed to analyze communication vulnerability to soft-errors and also to propose hardware designs to reduce this vulnerability as well as communication traffic. Currently, he is pursuing his Ph.D. (thesis title “Hardware Solutions to Accelerate Database Operation”) as a doctoral researcher at TUM. His research interests include computer‐aided design of very large‐scale integration (VLSI) circuits and systems, design and synthesis of system‐on‐chip, programmable systems, novel computer architectures, and highly scalable algorithm, parallel computing, high‐performance, and low‐power system design.